Computer architecture and the fetch–execute cycle

The Von Neumann model

A single memory holds both data and instructions; the CPU fetches and executes instructions one at a time.

Components of the CPU

• Arithmetic logic unit (ALU), control unit, system clock.
• Registers: program counter (PC – address of next instruction), memory address register (MAR), memory data register (MDR), current instruction register (CIR), accumulator (ACC), index register, status register.
• Buses: address bus (one-way, carries addresses), data bus (two-way), control bus (signals such as read/write, clock, interrupt).

The fetch–execute cycle (register transfer notation)

MAR ← [PC]; PC ← [PC] + 1; MDR ← [[MAR]]; CIR ← [MDR]; the instruction is decoded and executed. Interrupts are checked at the end of each cycle.

Performance factors

Clock speed, number of cores, cache size and bus width.

Assembly language and addressing modes

Opcode and operand; immediate (the value itself), direct (the address of the value), indirect, indexed and relative addressing. An assembler translates assembly language into machine code (two-pass assembler for labels).

Alternative architectures

Harvard (separate instruction and data memory), RISC versus CISC, pipelining, and parallel processing (SIMD, MIMD).

Check yourself

1. What does the program counter hold?
2. Which bus is bidirectional?
3. Give one advantage of RISC processors.